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1 of 52 semtech GV7704 preliminary data sheet rev.3 pds-060376 september 2015 GV7704 quad hd-vlc? receiver www.semtech.com key features ? quad channel serial digital video receiver for hd video surveillance and hdcctv applications ? dual rate operation: 270mb/s and 1.485gb/s ? supports hdcctv 1.0, hd-sdi (st 292) and sd-sdi (st 259)* ? four independent receiver channels with high performance cable equalization, with support for 50/75 coaxial and twisted pair cable transmission ? integrated high definition visually lossless codec (hd-vlc?) for extended cable reach: ? 550m over belden 543945 cctv coaxial cable ? 150m over cat-5e/6 utp cable ? serial digital loop-though output per channel ? integrated audio de-embedder for the extraction of up to 4 channels of i 2 s serial digital audio at 32khz, 44.1khz and 48khz sample ra tes, per video channel ? supports both 720p and 1080p hd formats: ? 1080p 25/29.97/30fps ? 720p 25/29.97/30/50/59.94/60fps ? four 8/10-bit bt.1120 compliant output video interfaces, with embedded trs and external hvf timing outputs ? automatic independent detection of hd-sdi and hd-vlc video input data streams per channel ? downstream ancillary data detection and extraction ? automatic hdcctv stream id detection ? 4-wire gennum serial peripheral interface (gspi 2.0) for external host command and control ? jtag test interface ? 1.2v core voltage power supplies ? 1.8v digital i/o power supply ? small footprint 169-bga (11mm x 11mm) ? low power operation, typically 810mw ? wide operating temperature range: -20c to + 85c ? pb-free and rohs compliant applications ? digital video recorders (dvr) ? video servers ? video multiplexers ? video pc capture cards ? hdcctv peripherals description the GV7704 is a quad channel serial digital video receiver for high definition component video. with integrated high performance cable equalizer technology, the GV7704 is capable of receiving hd video at 270mb/s and 1.485gb/s over 75 coaxial cable, or differentially over a 100 twisted pair cable. the GV7704 integrates the high definition visually lossless codec (hd-vlc?) technology, which has been developed specifically to reduce the tran smission data rate of hd video over both coaxial and un shielded twisted pair (utp) cable. this is achieved by encoding the hd video, normally transmitted at a serial data ra te of 1.485gb/s, to the same rate as standard definition (sd) video, at 270mb/s serial data rate. at 270mb/s, the effect of cable loss is greatly reduced, resulting in much longer cable transmission. for 75 coaxial cable, cable reach can be extended up to 3x the normal reach when transmitting encoded hd at 270mb/s. in typical video over coaxial in stallations, cable distances of up to 550m are possible. 550m belden 543945 coaxial cable gv7700 transmitter hd-vlc? camera hd-vlc? dvr hd video codec hdmi output hd-sdi or hd-vlc cameras GV7704 quad receiver image signal processor hd sensor gv7700 transmitter power sink power source rs422 rs422 in1 in2 in3 in4 150m cat-5e/6 cable hd-vlc? dvr hd-vlc? camera hdd storage GV7704 quad receiver coaxial cable application utp cable application hd at 270mb/s hd at 270mb/s
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 2 of 52 semtech www.semtech.com the GV7704 can also be conf igured to receive hd video over utp cable, such as cat-5e and cat-6 cable, when hd-vlc encoded at 270mb/s. the device supports the receptio n of both 8-bit and 10-bit per pixel ycbcr 4:2:2 bt.1120 component digital video. a single 10-bit wide parallel digital video output bus per channel is provided, with associated pixel clock and timing signal outputs. the GV7704 supports direct interfacing of hd video formats conforming to itu-r bt.709 and bt.1120-6 for 1125-line formats, and smpte st 296 for 750-line formats. the GV7704 supports the extracti on of ancillary data from the horizontal blanking of th e input video data stream. ancillary data packets can be accessed via the gspi, allowing downstream communication from the video source to sink device. the GV7704 recognizes data packets formatted in compliance with the hdcctv 2.0 communications protocol. the GV7704 features an audi o de-embedding core, which provides the extraction of up to 4 channels of i 2 s serial digital audio from the ancillary data space of the input video data stream. the audi o de-embedding core supports 32khz, 44.1khz, and 48khz sample rates. packaged in a space saving 169 ball 11 x 11mm bga, the GV7704 is ideal for high de nsity, multi-channel video recorder architectures. typi cally requiring only 810mw of power, the device does not requ ire any special heat sinking or air flow, reducing the over cost of hd dvr designs. *frame structure with encode d hd only. does not support sd/d1 video. functional block diagram GV7704 functional block diagram gspi sdin sclk sdout trst tdi tms tck tdo common digital control jtag ch0_dout[9:0] ch0_pclk ch0_aout_1_2 ch0_aout_3_4 ch0_aclk ch0_wclk ch1_dout[9:0] ch1_pclk ch1_aout_1_2 ch1_aout_3_4 ch1_aclk ch1_wclk ch2_dout[9:0] ch2_pclk ch2_aout_1_2 ch2_aout_3_4 ch2_aclk ch2_wclk ch3_sdi ch3_dout[9:0] ch3_pclk ch3_sdo ch3_aout_1_2 ch3_aout_3_4 ch3_aclk ch3_wclk rbias ch2_sdi ch1_sdi ch0_sdi ch2_sdo ch1_sdo ch0_sdo cdr s2p audio/ ancilliary extraction hdvlc decoder channel 3 channel 2 cdr eq s2p audio/ ancilliary extraction hdvlc decoder cdr s2p audio/ ancilliary extraction hdvlc decoder channel 1 cdr s2p output format audio/ ancilliary extraction hdvlc decoder format detect channel 0 ch3_sdi ch2_sdi ch1_sdi ch0_sdi reset cs ch0_sdo ch1_sdo ch2_sdo ch3_sdo output format format detect output format format detect output format format detect eq eq eq
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 3 of 52 semtech www.semtech.com revision history contents 1. pin out..................................................................................................................... ............................................5 1.1 GV7704 pin assignment ..................................................................................................... ..............5 1.2 pin descriptions .......................................................................................................... ........................6 2. electrical characteristics.................................................................................................. ........................... 13 2.1 absolute maximum ratings .................................................................................................. ...... 13 2.2 dc electrical characteristics ............................................................................................. ........... 14 2.3 ac electrical characteristics ............................................................................................. ............ 15 3. input/output circuits....................................................................................................... ........................... 16 4. detailed description........................................................................................................ ............................ 17 4.1 functional overview ....................................................................................................... ............... 17 4.2 serial digital inputs ..................................................................................................... .................... 17 4.2.1 input termination selection............................................................................................ 18 4.2.2 automatic signal rate detection .................................................................................. 18 4.3 serial digital outputs .................................................................................................... ................. 18 4.3.1 output signal interface levels ....................................................................................... 19 4.3.2 serial data output signal ................................................................................................ .19 4.4 video functionality ....................................................................................................... .................. 19 4.4.1 descrambling and word alignment ............................................................................ 19 4.4.2 hd-vlc decoding .......................................................................................................... ..... 20 4.4.3 high definition output video format ......................................................................... 21 4.5 parallel video data ou tputs chn_dout_[9:0] ..................................................................... 24 4.6 stream id packet extraction ............................................................................................... ......... 25 4.7 ancillary data extraction ................................................................................................. .............. 26 4.8 audio extraction .......................................................................................................... .................... 28 4.8.1 serial i2s audio data format .......................................................................................... 29 4.8.2 audio mute............................................................................................................... ............. 29 4.9 gspi host interface ....................................................................................................... .................. 30 version eco pcn date description 3 027518 september 2015 updated to preliminary data sheet. updated section 2.1 , section 2.2 , section 2.3 , section 4. , and figure 6-2 . added figure 6-3 . various updates throughout document. 2 027065 july 2015 updated cable reach values. updated table 2-2 and table 2-3 . 1 024435 march 2015 updated section 2.2 , section 2.3 , section 5. , and figure 6-1 . added section 3. , section 4.10 and section 4.11 . various updates throughout document. 0 021239 october 2014 new document
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 4 of 52 semtech www.semtech.com 4.9.1 cs pin ........................................................................................................................... ............ 30 4.9.2 sdin pin ................................................................................................................. ................. 30 4.9.3 sdout pin................................................................................................................ .............. 30 4.9.4 sclk pin ................................................................................................................. ................. 31 4.9.5 command word description .......................................................................................... 31 4.9.6 data word description.................................................................................................... .. 32 4.9.7 gspi transaction timing.................................................................................................. .33 4.9.8 single read/write access ................................................................................................. 34 4.9.9 auto-increment read/write access ............................................................................. 34 4.10 jtag ..................................................................................................................... .............................. 35 4.11 power supply and reset timing ............................................................................................ .. 36 5. register map................................................................................................................ ................................... 37 6. application information..................................................................................................... ........................ 47 6.1 typical application circuit ............................................................................................... ............ 47 7. packaging information ....................................................................................................... ........................ 49 7.1 package dimensions ........................................................................................................ .............. 49 7.2 recommended pcb footprint ................................................................................................. ... 50 7.3 marking diagram ........................................................................................................... .................. 50 7.4 solder reflow profile ..................................................................................................... ................. 51 7.5 packaging data ............................................................................................................ .................... 51 7.6 ordering information ...................................................................................................... ............... 51
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 5 of 52 semtech www.semtech.com 1. pin out 1.1 GV7704 pin assignment figure 1-1: GV7704 pin out ch3_sdi gnd ch3_sdo tck ch3_wclk ch2_wclk ch3_hout ch3_pclk ch3_dout_5 ch3_dout_3 ch3_dout_1 ch3_dout_0 gnd gnd vdd18_a tms ch3_aclk ch2_aclk ch3_vout ch3_dout_8 ch3_dout_6 ch3_dout_4 ch3_dout_2 ch2_vout n/c n/c vdd18_a tdi tdo ch3_aout_1_2 ch2_aout_1_2 ch3_fout ch3_dout_9 ch3_dout_7 ch2_hout ch2_fout ch2_pclk ch2_sdi gnd trst ext_fw ch3_aout_3_4 ch2_aout_3_4 gnd gnd gnd ch2_dout_9 ch2_dout_8 ch2_dout_7 gnd gnd vdd18_a vdd12_a rsvd gnd vdd18_d vdd18_d gnd gnd ch2_dout_6 ch2_dout_5 ch2_dout_4 ch2_sdo vdd18_a vdd12_a gnd vdd12_d vdd12_d vdd12_d vdd18_d gnd ch2_dout_3 ch2_dout_2 ch2_dout_1 gnd gnd vdd18_a vdd12_a gnd vdd12_d vdd12_d vdd12_d vdd18_d gnd gnd ch1_hout ch2_dout_0 ch1_sdo ch1_sdo vdd18_a vdd12_a gnd vdd12_d vdd12_d vdd12_d vdd18_d gnd ch1_vout ch1_fout ch1_pclk gnd gnd vdd18_a vdd12_a gnd gnd vdd18_d vdd18_d gnd gnd ch1_dout_9 ch1_dout_8 ch1_dout_7 ch1_sdi gnd rsvd ch0_wclk ch1_wclk gnd gnd gnd ch1_dout_6 ch1_dout_5 ch1_dout_4 rbias vdd18_a sdin sdout ch0_aclk ch1_aclk ch0_dout_2 ch0_dout_5 ch0_dout_8 ch1_dout_3 ch1_dout_2 ch1_dout_1 gnd gnd vdd18_a ch0_aout_1_2 ch1_aout_1_2 ch0_dout_1 ch0_dout_4 ch0_dout_7 ch0_dout_9 ch0_vout ch1_dout_0 ch0_sdi gnd ch0_sdo sclk ch0_aout_3_4 ch1_aout_3_4 ch0_dout_0 ch0_dout_3 ch0_dout_6 ch0_pclk ch0_hout ch0_fout 12345678910111213 a b c d e f g h j k l m n ch3_sdi ch2_sdi ch2_sdo ch1_sdi ch0_sdi ch3_sdo reset ch0_sdo cs gnd
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 6 of 52 semtech www.semtech.com 1.2 pin descriptions table 1-1: GV7704 pin descriptions pin number name type description analog high-speed inputs n1, n2 ch0_sdi, ch0_sdi analog high-speed input differential high-speed data input 0. (75 nominal input impedance) k1, k2 ch1_sdi, ch1_sdi analog high-speed input differential high-speed data input 1. (75 nominal input impedance) d1, d2 ch2_sdi, ch2_sdi analog high-speed input differential high-speed data input 2. (75 nominal input impedance) a1, a2 ch3_sdi, ch3_sdi analog high-speed input differential high-speed data input 3. (75 nominal input impedance) analog high-speed outputs n4, m4 ch0_sdo, ch0_sdo analog high-speed output differential high-speed test output 0. (75 nominal output impedance) h1, h2 ch1_sdo, ch1_sdo analog high-speed output differential high-speed test output 1. (75 nominal output impedance) f1, f2 ch2_sdo, ch2_sdo analog high-speed output differential high-speed test output 2. (75 nominal output impedance) a4, b4 ch3_sdo, ch3_sdo analog high-speed output differential high-speed test output 3. (75 nominal output impedance) analog bias l1 rbias input/output external 10k resistor for bias reference. connect the resistor to ground. digital video outputs l8, l9, l10, m8, m9, m10, m11, n8, n9, n10 ch0_dout_[9:0] output parallel digital video output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg.
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 7 of 52 semtech www.semtech.com n12 ch0_hout output horizontal blanking output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. m12 ch0_vout output vertical blanking output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. n13 ch0_fout output frame indication output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. n11 ch0_pclk output pixel clock output (148.5mhz or 148.5/1.001 mhz). high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. j[11:13], k[11:13], l[11:13], m13 ch1_dout_[9:0] output parallel digital video output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. g12 ch1_hout output horizontal blanking output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. h11 ch1_vout output vertical blanking output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. h12 ch1_fout output frame indication output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. table 1-1: GV7704 pin desc riptions (continued) pin number name type description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 8 of 52 semtech www.semtech.com h13 ch1_pclk output pixel clock output (148.5mhz or 148.5/1.001 mhz). high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. d[11:13], e[11:13], f[11:13], g13 ch2_dout_[9:0] output parallel digital video output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. c11 ch2_hout output horizontal blanking output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. b13 ch2_vout output vertical blanking output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. c12 ch2_fout output frame indication output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. c13 ch2_pclk output pixel clock output (148.5mhz or 148.5/1.001 mhz). high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. a[10:13], b[9:12], c9, c10 ch3_dout_[9:0] output parallel digital video output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. a8 ch3_hout output horizontal blanking output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. table 1-1: GV7704 pin desc riptions (continued) pin number name type description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 9 of 52 semtech www.semtech.com b8 ch3_vout output vertical blanking output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. c8 ch3_fout output frame indication output. high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. a9 ch3_pclk output pixel clock output (148.5mhz or 148.5/1.001 mhz). high impedance when signal is not present or user disables the lane (disable_video_lane). drive strength may be adjusted using register parallel_video_out_drv_strength_sel_reg. digital audio outputs k6 ch0_wclk output channel 0 word clock (32khz, 44.1khz, or 48khz). high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). l6 ch0_aclk output channel 0 i 2 s audio clock (64 x word clock). high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). m6 ch0_aout_1_2 output channel 0 i 2 s audio output 1 & 2. high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). n6 ch0_aout_3_4 output channel 0 i 2 s audio output 3 & 4. high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). k7 ch1_wclk output channel 1 word clock (32khz, 44.1khz, or 48khz). high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). l7 ch1_aclk output channel 1 i 2 s audio clock (64 x word clock). high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). table 1-1: GV7704 pin desc riptions (continued) pin number name type description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 10 of 52 semtech www.semtech.com m7 ch1_aout_1_2 output channel 1 i 2 s audio output 1 & 2. high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). n7 ch1_aout_3_4 output channel 1 i 2 s audio output 3 & 4. high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). a7 ch2_wclk output channel 2 word clock (32khz, 44.1khz, or 48khz). high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). b7 ch2_aclk output channel 2 i 2 s audio clock (64 x word clock). high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). c7 ch2_aout_1_2 output channel 2 i 2 s audio output 1 & 2. high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). d7 ch2_aout_3_4 output channel 2 i 2 s audio output 3 & 4. high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). a6 ch3_wclk output channel 3 word clock (32khz, 44.1khz, or 48khz). high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). b6 ch3_aclk output channel 3 i 2 s audio clock (64 x word clock). high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). c6 ch3_aout_1_2 output channel 3 i 2 s audio output 1 & 2. high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). d6 ch3_aout_3_4 output channel 3 i 2 s audio output 3 & 4. high impedance when signal is not present or user disables the lane (disable_video_lane) or user disables audio (disable_audio). table 1-1: GV7704 pin desc riptions (continued) pin number name type description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 11 of 52 semtech www.semtech.com jtag interface b5 tms input dedicated jtag pin C test mode select. this pin is used to control the operation of the jtag test. schmitt trigger input with pull-up. if jtag is not used this pin may be left floating. c4 tdi input dedicated jtag pin C test data input. this pin is used to shift jtag test data into the device. schmitt trigger input with pull-up. if jtag is not used this pin may be left floating. c5 tdo output dedicated jtag pin C test data output. this pin is used to shift results from the device. a5 tck input dedicated jtag pin C serial data clock signal. this pin is the jtag clock. schmitt trigger input. if jtag is not used this pin must be pulled low. d4 trst input dedicated jtag pin C test reset. when set low, the jtag logic will be reset. schmitt trigger input with pull-up. if jtag is not used this pin must be pulled low. general i/o and host interface k4 reset input digital activeClow reset input. used to reset the internal. operating conditions to default settings. schmitt trigger input. m5 cs input used to initiate and terminate gspi commands. active-low. l4 sdin input serial input data, clocked in on the rising edge of sclk. l5 sdout output serial data output. only used in gspi mode. clocked out on the falling edge of sclk. drive strength may be adjusted using register gspi_sdout_drv_strength_sel_reg. n5 sclk input serial clock. the rising edge is used to latch the sdin bits and the falling edge to drive sdout bits. d5 ext_fw input external firmware loading control: when high, indicates to the GV7704 that the host will download firmware to the GV7704. when low, indicates to the GV7704 to boot with internal firmware. table 1-1: GV7704 pin desc riptions (continued) pin number name type description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 12 of 52 semtech www.semtech.com supply pins b3, c3, e3, f3, g3, h3, j3, l2, m3 vdd18_a power analog 1.8v power supply. connect to 1.8v. e7, e8, f9, g9, h9, j7, j8 vdd18_d power digital 1.8v power supply. connect to 1.8v. e4, f4, g4, h4, j4 vdd12_a power analog 1.2v power supply. connect to 1.2v. f6, f7, f8, g6, g7, g8, h6, h7, h8 vdd12_d power digital 1.2v power supply. connect to 1.2v. a3, b1, b2, d3, d8, d9, d10, e1, e2, e6, e9, e10, f5, f10, g1, g2, g5, g10, g11, h5, h10, j1, j2, j5, j6, j9, j10, k3, k8, k9, k10, l3, m1, m2, n3 gnd power connect to gnd. c1, c2 n/c do not connect. e5, k5 rsvd connect to gnd. table 1-1: GV7704 pin desc riptions (continued) pin number name type description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 13 of 52 semtech www.semtech.com 2. electrical characteristics 2.1 absolute maximum ratings table 2-1: absolute maximum ratings parameter value 1.8v i/o and analog supply voltage C0.5v to +2.5v dc 1.2v analog and core supply voltage C0.3v to +1.5v dc dc input voltage, vin (not to exceed 2.5v) C0.5v to (vdd18 + 0.5v) dc output voltage, vout (not to exceed 2.5v) C0.5v to (vdd18 + 0.5v) input esd voltage (hbm) 2kv input esd voltage (cdm) 500v storage temperature range (t s ) -50c to 125c operating temperature range (t a ) -20c to 85c solder reflow temperature (4s) 260c note: absolute maximum ratings are those values beyond which damage may occur. functional operation outside of the ranges shown in the ac and dc electrical characteristics is not guaranteed.
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 14 of 52 semtech www.semtech.com 2.2 dc electrical characteristics table 2-2: dc electrical characteristics t a = -20c to +85c unless otherwise stated parameter symbol conditions min typ max units notes +1.2v supply current i 1v2 270mb/s 172 ma 1.485gb/s 250 ma +1.8v supply current i 1v8 270mb/s 440 ma 1.485gb/s 456 ma +1.8v power supply range vdd18 at the device pin (nominal 5%) 1.71 1.8 1.89 v +1.2v power supply range vdd12 at the device pin (nominal 5%) 1.14 1.2 1.26 v external rbias resistor 9.9 10 10.1 k power supply noise mask +1.2v 0-200khz 100 mv pp 1 200khz to 1mhz 100 mv pp 1 >1mhz 100 mv pp 1 power supply noise mask +1.8v 0 to 200khz 10 mv pp 1 200khz to 1mhz 30 mv pp 1 >1mhz 100 mv pp 1 total power consumption p total 270mb/s, all cable drivers enabled 950 1030 mw 270mb/s, all cable drivers disabled 810890mw 1.485gb/s, all cable drivers enabled 1070 1160 mw 1.485gb/s, all cable drivers disabled 900990mw digital logic input v il input low -0.3 0.63 v v ih input high 1.17 1.89 v digital logic output v ol output low 0.45 v 2 v oh output high 1.35 v 2 c load 148.5mhz 12 pf notes: 1. using recommended supply decoupling. see figure 6-1: typical application circuit (part 1) . 2. all digital outputs.
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 15 of 52 semtech www.semtech.com 2.3 ac electrical characteristics table 2-3: ac electrical characteristics vdd18_a, vdd18_d = 1.8v5% and t a = -20c to +85c unless otherwise stated parameter symbol conditions min typ max units notes input conditions sdi input termination (on chip) 50 75 input return loss 1mhz to 5mhz 23 db 5mhz to 1.485ghz 12 db 1.485ghz to 2.25ghz 10 db clock and data output conditions output pclk clock frequency f pclk 148.5 or 148.5/ 1.001 mhz sdo output impedance 75 single-ended 66 75 84 100 differential 88 100 112 output return loss 1mhz to 5mhz 25 db 5mhz to 1.485ghz 6 db 1.485ghz to 2.25ghz 6 db amplitude 75 single-ended 0.36 0.8 0.9 v pp 100 differential 0.36 0.8 0.9 v ppd rise/fall time 20% to 80% 130 150 ps rise/fall time matching 20% to 80% 15 ps overshoot 10 % output total jitter data rate = 270mb/s 0.08 ui pp data rate = 1.485gb/s 0.11 ui pp gspi digital control gspi read/write clock frequency 55mhz reset time 10 ms register access time 300 ns
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 16 of 52 semtech www.semtech.com 3. input/output circuits figure 3-1: rbias figure 3-2: serial output driver figure 3-3: serial input receiver rbias to clamp 50/75 output drive impedance level & de-emphasis control level & de-emphasis control ch[0:3]_sdo_n ch[0:3]_sdo_p gnd esd clamp 1.8v vdda18_drv 50/75 receiver termination esd clamp ch[0:3]_sdi_n ch[0:3]_sdi_p
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 17 of 52 semtech www.semtech.com 4. detailed description 4.1 functional overview the GV7704 is a low cost, quad cha nnel hd-vlc receiver of compressed or uncompressed high-definition video. with in tegrated cable equalizer technology, the GV7704 is capable of receiving hd vid eo at 270mb/s and 1.485gb/s over 75 coaxial cable, or differentially over a 100 twisted pair cable. the high definition visually lossless codec (hd-vlc?) technology is integrated in order to reduce the transmission data rate of hd video over both coaxial and unshielded twisted pair (utp) cable. this is achieved by encoding the hd-sdi video, normally transmitted at a serial data rate of 1.485gb/ s, to the same rate as standard definition (sd-sdi) video, at 270mb/s serial data rate. this provides extended cable reach for hd video up to 550m over belden 543945 cctv coax or 150m over cat-5e/6 utp cable. the GV7704 features an audio de-embedding core, which provides the extraction of up to 4 channels of i 2 s serial digital audio from the ancillary data space of the input video data stream. the audio de-emb edding core supports 32kh z, 44.1khz an d 48khz sample rates. the device supports the reception of both 8-bit and 10-bit per pixel ycbcr 4:2:2 bt.1120 component digital video. a single 10-bit wide parallel digital video output bus per channel is provided, with associated pixel clock and h/v/f timing signal inputs. the GV7704 supports the extrac tion of ancillary data from the horizontal blanking of the input video data stream. ancillary data pack ets can be accessed via the gspi, allowing downstream communication from the vide o source to sink device. the GV7704 recognizes data packets formatted in compl iance with the hdcctv 2.0 communications protocol. the device includes a 4-wire gennum serial peripheral interface (gspi 2.0) for external host command and control. all read or write access to the GV7704 is initiated and terminated by the application host processor. the host interface is provided to allow optional configuration of some of the functions and operating modes of the GV7704. 4.2 serial digital inputs the GV7704 can accept up to four separate channels of serial digital input signals compliant with itu-r bt.709, and itu-r bt.1120-6. the four differential input channels are ch0_sdi/ch0_sdi , ch1_sdi/ch1_sdi , ch2_sdi/ch2_sdi and ch3_sdi/ch3_sdi . the GV7704 integrates adaptive 75 coaxial cable equalize r technology which is capable of >50db for hd-vlc encoded inpu t signals and >35db for hd uncompressed signals.
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 18 of 52 semtech www.semtech.com the serial data signal may be connected to the input pins of any of the four channels in either a differential or single ended configur ation. only ac coupling of the inputs is supported, as the sdi and sdi inputs are internally biased at approximately 1.8v. note: the serial data output should be disa bled to achieve maximum sdi cable reach. 4.2.1 input termination selection each of the four channels can be individuall y configured to work in either 50 or 75 input termination. please refer to register map for details. 4.2.2 automatic signal rate detection the device is able to automatically detect the rate of the incoming video signal. there are two data rates which are supported: ? hd-vlc encoded 270mb/s (including 270x1.001mb/s) ? hd-sdi 1.485gb/s (including 1.4851.001gb/s) the detected rate is indicated in bit sd_h db in register gen_video_cfg_0_reg which specify whether the incoming signal is hd-vlc encoded (270mb/s) or hd (1.485gb/s). 4.3 serial digital outputs the GV7704s serial data output pins, sdo and sdo , provide complementary outputs, each capable of driving at least 80 0mv into a 75 single-ended load. compliance with all requirements defined in section 4.3.1 through section 4.3.2 is guaranteed when measured across a 75 terminated load at the output of 1m of belden 543945 cable, including the effects of the bnc and coaxial cable connection, except where otherwise stated. figure 4-1 illustrates this requirement. figure 4-1: bnc and co axial cable connection table 4-1: typical cable length performance data rate belden 543945 cctv coaxial cat-5e/6 utp hd data @ 1.485gb/s 150m n/a hd-vlc encoded data @ 270mb/s 550m 150m bnc 1m belden 543945 75 coaxial cable 75 resistive load measuring device bnc coupling capacitor GV7704
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 19 of 52 semtech www.semtech.com 4.3.1 output signal interface levels the serial data output signals (sdo and sdo pins), of the device meet the amplitude requirements as defined in itu-r bt.656 and bt.1120 for an unbalanced generator (single-ended). these requirements are met across all ambient temperature and power supply operating conditions described in 2. electrical characteristics . 4.3.2 serial data output signal the device supports two output terminatio n modes (75 and 50 ). the user can program the sdo_50_en_reg to make that se lection, on a per ch annel basis. please refer to register map for details. 4.3.2.1 serial data outp ut signal procedure to enable the serial data output, the user must do a series of gspi write transactions. the order is very important and must be followed exactly. the sequence is as shown below: 1. write 03 to the power_up_driver_reg 2. write 01 to the p2s_clk_en_reg 3. write 01 to the tx_word_clk_enable_reg 4. write 01 to the cdr_tx_clk_en_reg 5. write 01 to the p2s_rstb_reg 6. write 09 to the datalane_fifo_ctrl_reg 7. write 08 to the datalane_fifo_ctrl_reg please refer to section 5. register map for detailed register information. refer to section 4.9 for gspi timing requirements. note: the serial data output should be disabled to achieve maximum sdi cable reach. 4.4 video functionality 4.4.1 descrambling and word alignment the GV7704 performs nrzi to nrz decoding and data descrambling according to itu-r bt.1120, and word aligns the data to trs sync words. the GV7704 carries out descrambling and wo rd alignment to enable the detection of trs sync words. when two consecutive valid trs words (sav and eav), with the same bit alignment have been detected, the device word-aligns the data to the trs id words. note : both 8-bit and 10-bit trs head ers are identified by the device.
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 20 of 52 semtech www.semtech.com 4.4.2 hd-vlc decoding the GV7704 integrates the high definition visually lossless co dec (hd-vlc) decoder for extended reach video reception. when used in conjunction with the gv7700 hd-vlc transmitter, hd video transmissi on can be extended significan tly over existing hd serial digital video systems. hd-vlc is based on a simple visually lossless implementation of the dirac compression tool kit ( http://dirac video.org/ ) the visually lossless decoder is used to reduce the video bandwidth, using a very low latency mode, from a transmission rate of 1.485gb/s (hd-sdi) to 270mb/s (sd-sdi). at a data rate of 270mb/s, the serial digi tal encoded hd video ca n be transmitted over longer runs of coaxial cable. table 4-2 below shows a comparison of cable distances between hd video transmission at 1.485g b/s and hd-vlc encoded at 270mb/s for various common coaxial cable types. note: the serial data output should be disa bled to achieve maximum sdi cable reach. after transmission over the coaxial cable, the 270mb/s serial data is recovered using the GV7704 and the data is decoded back into the native hd format. the encoding and decoding process has a total latency of 12-1 4 hd lines, which make s the codec ideal for low latency real-time applications. table 4-3 below shows the total encode/decode latency through the GV7704 and the gv7700. table 4-2: cable reach for various cable types (in metres) cable type hd-vlc: 270mb/s (m) hd-sdi: 1.485gb/s (m) belden 1694a / canare l-4.5chd 710 230 belden 543945 550 150 kw-link syv 75-5 500 140 canare l-3c2v 300 95 kw-link syv 75-3 300 85 note: these values apply for new, properly terminated cables. actual performance may vary. table 4-3: encode and decode total latency (GV7704 + gv7700) video format delay (s) delay (hd lines) 1080p25 422.2 11.9 1080p29.97 368.8 12.4 1080p30 368.4 12.4 720p25 635.1 11.9 720p29.97 546.6 12.2 720p30 546.6 12.2 720p50 368.6 13.8 720p59.94 324.2 14.5 720p60 324.2 14.5
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 21 of 52 semtech www.semtech.com the 270mb/s data stream uses the same timing and frame structure as standard definition sdi (sd-sdi), and can be monitore d using standard sd-sdi test equipment to check signal integrity. however, the data contained within the active picture area of the sd-sdi stream contains only encoded hd packets. the hd video content can only be viewed after the hd-vlc decoding process. when the GV7704 is hd-vlc encoding hd video formats at true 30 or 60 frames per second, the 270mb/s serial data input wi ll actually be incoming at a rate of 270 x 1.001mb/s. this multiplica tion factor is to account for the fractional increase in the original hd video frame rate. for all other hd frame rates, the incoming serial data will be exactly 270mb/s. 4.4.3 high definition output video format itu-r bt.1120 describes the serial and parallel format for 1080-line interlaced and progressive digital video. the field/frame bl anking period (v), the line blanking period (h), and the field identification (f), are e mbedded as digital timing codes (trs) within the video. after deserialization, a single 10-bit bus carrying the c'b, y', c'r, y', etc. data pattern is output on the 10-bit parallel data interface, operating at a pixel clock rate of 148.5mhz or 148.5/1.001 mhz. the following figures show horizontal and vertical timing for 1080-line interlaced systems. figure 4-2: field timing relationship for 1080-line interlaced systems blankin g blankin g 1 blankin g blankin g 20 21 560 561 563 564 583 584 1123 1124 1125 field 1 a c tive video v=0 v=1 field 1 (f=0) odd h=1 eav field 2 (f=1) even h=0 s av field 2 a c tive video v=1 v=0 v=1 line
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 22 of 52 semtech www.semtech.com figure 4-3: multiplexed luma and ch roma over one video line - 1080i 4.4.3.1 high defi nition 1080p output formats itu-r bt.1120 also includes pr ogressive scan formats with 10 80 active lines, with y'c' b c' r 4:2:2 sampling at pixel rates of 74.25mhz or 74.25/1.001 mhz. the following diagrams show horizontal and vertical timing for 1080-line progressive systems. the GV7704 provides a 10-bit multiplexed output interface, doubling th e pixel clock output rate to 148.5mhz or 148.5/1.001 mhz. figure 4-4: frame timing relationshi p for 1080-line progressive systems figure 4-5: multiplexed luma and ch roma over one video line - 1080p table 4-4: 1080-line interlaced horizontal timing interlaced 60 or 60/1.001 hz 50hz h1 560 1440 h2 4400 5280 start of digital line eav code sav code blanking start of digital active line next line multiplexed stream 3ff 000 xyz ln0 ccr0 ln1 000 000 000 3ff 3ff xyz ycr0 3ff 000 000 3ff 000 000 xyz ln0 ln1 3ff xyz ccr1 ycr1 ca0 ya0 ca1 ya1 ca2 ya2 ca(n-1) ya(n-1) cbd0 yd0 crd0 yd1 cbd1 yd2 cbd959 yd1918 crd959 yd1919 1920 h1 h2 a c tive video blankin g blankin g 1 41 42 1121 1122 1125 v=0 v=1 (f=0) h=1 eav h=0 s av v=1 line start of digital line eav code sav code blanking start of digital active line next line multiplexed stream 3ff 000 xyz ln0 ccr0 ln1 000 000 000 3ff 3ff xyz ycr0 3ff 000 000 3ff 000 000 xyz ln0 ln1 3ff xyz ccr1 ycr1 ca0 ya0 ca1 ya1 ca2 ya2 ca(n-1) ya(n-1) cbd0 yd0 crd0 yd1 cbd1 yd2 cbd959 yd1918 crd959 yd1919 1920 h1 h2
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 23 of 52 semtech www.semtech.com 4.4.3.2 high defi nition 720p output formats the society of motion picture and television engineers (smpte) defines the standard for progressive scan 720-line hd image form ats. smpte st 296-2001 specifies the representation for 720p digital y'c' b c' r 4:2:2 signals at pixel rates of 74.25mhz or 74.25/1.001 mhz. the GV7704 provides a 10-bit multiplexed output interface, doubling the pixel clock output rate to 148.5mhz or 148.5/1.001 mhz. figure 4-6: 720p digital vertical timing the frame rate determines the horiz ontal timing, which is shown in table 4-6 . 4.4.3.3 bt.656 video output timing mode by default, the 10-bit parallel video output will contain two embedded trs words, as defined in itu-r bt.1 120. some commercially available codec devices cannot detect the presence of the double trs in the hd video stream, and require that the 8/10-bit hd video contain only one trs word, as per the itu-r bt.656 standard definition format. when the bt656_enable bit is high, the GV7704 will re-format the parallel video output to conform with bt.656 embedded trs. the device will replace all data words table 4-5: 1080-line progressive horizontal timing progressive 30 or 30/1.001 hz 25hz 24 or 24/1.001 hz h1 560 1440 1660 h2 4400 5280 5500 a c tive video blankin g blankin g 1 25 26 745 746 750 v=0 v=1 (f=0) h=1 eav h=0 s av v=1 line table 4-6: 720p horizontal timing frame rate h = 1 sample number h = 0 sample number total samples per line 25 2560 0 7920 30 or 30/1.001 2560 0 6600 50 2560 0 3960 60 or 60/1.001 2560 0 3300
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 24 of 52 semtech www.semtech.com from the second trs, line number and line crc with blanking values, as shown in figure 4-7 . note that when bt.656 output mode is enabled, any embedded ancillary data in the horizontal balking will remain unchanged, and will no t be contiguous from the eav. this is shown in figure 4-8 below. figure 4-7: bt.656 video output timing figure 4-8: ancillary data in bt.656 video output timing mode 4.5 parallel video data outputs chn_dout_[9:0] a 10-bit video output bus is provided for ea ch received video channe l. the parallel data outputs are aligned to the rising edge of pclk. each output provides a 10-bit multiplexed itu-r bt.1120 compliant video bu s with embedded trs. the drive strength of the parallel video output pins (pclk, hout, vout, fout , dout[9:0]) can be adjusted using the parallel_video_out_drv_stren gth_sel bit. the device uses the low drive strength setting by default. for pcb trace longer than 6 inches the high drive strength setting should be used. figure 4-9: GV7704 parallel vi deo output timing diagram chn_pclk chn_dout_[9:0] 000 h eav 040 h 040 h 200 h 200 h 200 h 200 h 040 h y, n-1 y, n-2 y, n-3 y, n-4 3ff h 000 h 200 h 200 h 040 h 040 h 040 h 040 h 200 h cr, n-2 cb, n-2 cr, n-4 cb, n-4 chn_hout chn_vout chn_fout 040 h 200 h 200 h 040 h 040 h 000 h sav 200 h 200 h 3ff h 000 h 040 h 200 h y, 3 y, 2 y, 1 y, 0 cr, 2 cb, 2 cr, 0 cb, 0 y, 7 y, 6 y, 5 y, 4 cr, 6 cb, 6 cr, 4 cb, 4 y, 9 y, 8 cb, 10 cr, 8 cb, 8 chn_dout_[9:0] chn_hout inserted blanking words inserted blanking words chn_dout_[9:0] 040 h 040 h 040 h 040 h 000 h 3ff h 040 h 040 h eav 000 h 200 h 200 h 200 h 200 h 040 h 040 h 040 h 200 h 200 h 000 h 3ff h inserted blanking words 3ff h ancillary data data_1 transition zone data_1 data_0 transition zone chn_pclk pclk period chn_dout[9:0], chn_fout, chn_hout, chn_vout data_0 t h data_* is launched on the positive edge of pclk t od t od t su t h data_0 transition zone
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 25 of 52 semtech www.semtech.com 4.6 stream id packet extraction the GV7704 will automatically detect and extr act hdcctv stream id packets from all four video channels. each channel s 6 byte packet can be read from the host interface through the bits extract_stream_i d_byte[1:6] located in registers extract_stream_id_reg[1:6] respectively. there are independent registers for each of the four channels. when the GV7704 is decoding hd-vlc streams, the device will automatically re-insert the correct stream id in the hd parallel vid eo output. only bytes 1 and 2 of the stream id packet will be updated, with all other by tes set to all zero. the re-inserted byte 1 and 2 data can be read from registers ins_id _byte1_reg and ins_id _byte_2_reg. bytes 1 and 2 can be programmed from bits ins_id_byte[1:2] located in registers ins_id_byte_reg[1: 2] respectively. byte 1 of the stream id packet is inte rpreted according to table 4-8 below. table 4-7: digital outp ut specifications digital parallel video output interface symbol conditions min typ max units notes parallel clock frequency f pclk 148.5 mhz parallel clock duty cycle dc pclk 4060% output data hold time (hd) t oh 1.89v operation, 6pf c load , 0c 1.0 ns output data delay time (hd) t od 1.71v operation, 6pf c load , 85c 3.7ns output data rise/fall time (hd) t r /t f 1.89v operation, 6 pf c load , 0c 0.4ns 1.71v operation, 15 pf c load , 85c 1.4ns table 4-8: stream id packet extraction byte 1 input video standard hd-vlc encoding byte 1 value original video standard 720p25 off 14h 720p25 625i25 on 94h 720p25 720p29.97 off 12h 720p29.97 525i29.97 on 92h 720p29.97 720p30 off 11h 720p30 525i30 on 91h 720p30 1080i50 off e3h 1080i50
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 26 of 52 semtech www.semtech.com note: when the GV7704 is receiving hd-vlc en coded hd video format s at "true" 30 or 60 frames per second, the 270mb/s serial data rate will be at 270 x 1.001 mb/s. this multiplication factor is to account for the fr actional increase in the original hd video frame rate. for all other hd frame rates, the hd-vlc encoded serial data rate will be exactly 270mb/s. 4.7 ancillary data extraction the GV7704 is capable of extracting ancillary data packets, with the type of packet specified by the user on a pr ogrammable 10 bit did. the 2 msbs of the did are written to anc_packet_did_9_8 in register anc_ packet_did_9_8_reg, and the next 8 bits are written to anc_packet_did_7_0 in register anc_packet_did_7_0_reg. up to 16 user data words can be extracte d per ancillary data packet. the chip will extract the did-sdid/dbn-dc-udws-cs bytes, and they are available in 10-bit pairs (anc_packet_ud w0_9_8, anc_packet_udw0_7_0) through to (anc_packet_ud w15_9_8, anc_packet_udw15_7_0). 720p50 off 13h 720p50 625i25 on 93h 720p50 1080i59.94 off e2h 1080i59.94 720p59.94 off 16h 720p59.94 525i29.97 on 96h 720p59.94 1080i60 off e1h 1080i60 720p60 off 15h 720p60 525i30 on 95h 720p60 1080p25 off 23h 1080p25 625i25 on a3h 1080p25 1080p29.97 off 22h 1080p29.97 525i29.97 on a2h 1080p29.97 1080p30 off 21h 1080p30 525i30 on a1h 1080p30 625i25 on f3h 1080i50 525i29.97 on f2h 1080i59.94 525i30 on f1h 1080i60 table 4-8: stream id packet extraction byte 1 (continued) input video standard hd-vlc encoding byte 1 value original video standard
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 27 of 52 semtech www.semtech.com the GV7704 looks for packets in the horizontal blanking region of a digital video signal. the vertical blanking region is used by the hd-vlc encoder of the gv7000 which inserts compression coefficients that cannot be over written. the payload of the ancillary data packet can be used to carry user-defined or proprietary data, which can be sent between an aviia transmitter and receiver. the ancillary data packet is formatted according to the figure 4-10 below. the packet must always begin with the ancillary data flag (adf), defined as the following 10-bit word sequence: 000 h , 3ff h , 3ff h . the next data word is the 8-bit data id (did), used to define the contents of the packet. for example, a unique did ca n be used to denote alarm data, with another did to denote status data. after the did, there are two possible options, as shown in figure 4-10 . figure 4-10: ancillary data packets a type 1 packet defines an 8-bit data block number (dbn) sequence, used to distinguish successive packets with the same did. the dbn simply increments with each packet of the same did, between 0 and 15. for a type 2 packet, an 8-bit secondary data id (sdid) word is defined, which can be used to denote variants of payloads with the same did. for example, packets with a did to denote error data may distinguish different error types using unique sdid's. after the dbn or sdid, the next data word is the 8-bit data count (dc). this word must be set to the number of user data words (u dw) that follow the dc, and must not exceed 16 (maximum payload size). the final word of the ancillary data packet is the 9-bit checksum (cs). the cs value must be equal to the nine least sign ificant bits of the sum of the nine least significant bits of the did, the dbn or the sdid , the dc and all user data words (udw) in the packet. for hd video formats, ancillary data packet s are only extracted fr om the luma channel. user data words msb lsb parity bit type 1 ancillary data packet user data words not b8 parity bit type 2 ancillary data packet msb lsb not b8 adf did dbn dc udw0 udw1 udw2 udw3 cs adf did sdid dc cs udw14 udw13 udw12 udw11 udw10 udw9 udw8 udw7 udw 6 udw5 udw4 udw15 udw0 udw1 udw2 udw3 udw14 udw13 udw12 udw11 udw10 udw9 udw8 udw7 udw 6 udw5 udw4 udw15
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 28 of 52 semtech www.semtech.com 4.8 audio extraction the GV7704 will de-embed audio from both hd and hd-vlc enco ded data. the GV7704 can extract up to four channels of serial digi tal audio at an audio sampling rate of 32khz, 44.1khz, or 48khz. by default, audio extraction for each channel is enabled, and it can be disabled on any channel by setting disable_audio to 01 in the audio_ctrl_overrride_reg register from the host interface. by default, the device will process audio at a sampling rate of 48khz. when using a gv7700 to GV7704 chip set, audio sampled at 44.1khz and 32khz will be automatically detected by the GV7704. the GV7704 reads the stream id packet byte 3 to determine the audio sampling frequency. when receiving from a signal not transmitte d by the gv7700, the audio sampling rate must be manually specified if differ ent than 48khz, first by setting audio_samp_freq_manual_mode to 1, an d then by specifying the sampling frequency through audio_samp_freq. refer to table 4-9 below. the device will continuously look for th e programmable audio group did and updates the audio packets present on every rising edge of the vertical blanking interval. if several audio groups are present in the video signal, the device will extract the lower audio group number (ex: audio group 2, audio grou p 8: audio group 2 will be extracted). as such, the programmable audio group did is offered to the user as a method of selecting the audio group of his choice for extraction or for specifying an audio did that would be different from the 8 hd audio group dids specified in the smpte standards. the audio packet format is smpte st 299-1, regardless of the input signal rate (270mb/s or 1.485gb/s). the GV7704 will compute ecc (error correcting codes) and compare them to the ecc embedded in the audio packets, and it will correct errors wherever possible as well as report any errors found. error correction can be disabled by setting disable_ecc to 01 in the aud_ext_config_reg register, and the audio samples will be bypassed as found in the packets. the audio samples will be buffered and output on the four i 2 s channels via chn_aclk, chn_wclk, chn_ain_1_2, and chn_ain_3_4 pins. they will be formatted according to the standard i 2 s bus specifications, and the timing for this interface is shown in figure 4-11 below. table 4-9: register settings for manual audio sampling frequency audio_samp_freq sampling frequency 00 (default) 48khz 01 44.1khz 10 32khz 11 reserved
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 29 of 52 semtech www.semtech.com figure 4-11: aclk to audio data and wclk signal output timing 4.8.1 serial i 2 s audio data format the GV7704 supports the i 2 s serial audio data format, as shown in figure 4-12 below. figure 4-12: i 2 s audio output format 4.8.2 audio mute the GV7704 can mute either pair of output audio channels using 2 host interface control bits for each video lane. the bits can mute channels 0 & 1 or channels 2 & 3. channels 0 & 1 can be muted by asserting the mute 0_ 1 bit in the aud_ext_config_reg for any of the four video lanes. channels 2 & 3 can be muted by asserting the mute_2_3 bit in the aud_ext_config_reg for any of the four video lanes. see table 4-11 . by default, the 4 channels will not be muted. chn_aclk data chn_aout_0_1, chn_aout_2_3 chn_wclk data not to scale t oh t od 48khz audio: 325.5ns 44.1khz audio: 354.3ns 32khz audio: 488.3ns table 4-10: GV7704 serial audio data outp uts - ac electrical characteristics parameter symbol conditions min typ max units output data hold time t oh 50% levels; 1.8v operation 1.5 ns output data delay time t od 7.0 ns chn_wclk chn_aclk chn_ain_0_1/chn_ain_2_3 msb 6 22 lsb channel a (left) channel b (right) 23 54321 0 6 22 lsb 54321 0 23 msb
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 30 of 52 semtech www.semtech.com 4.9 gspi host interface the GV7704 is controlled via the gennum serial peripheral interface (gspi). the gspi host interface is comprised of a seri al data input signal (s din pin), serial data output signal (sdout pin), an active-low chip select (cs pin) and a burst clock (sclk pin). the GV7704 is a slave device, so the sclk, sdin and cs signals must be sourced by the application host processor. all read and write access to the device is in itiated and terminated by the application host processor. 4.9.1 cs pin the chip select pin (cs ) is an active-low si gnal provided by the host processor to the GV7704. the high-to-low transition of this pin mark s the start of serial communication to the GV7704. the low-to-high transition of this pin mark s the end of serial communication to the GV7704. 4.9.2 sdin pin the sdin pin is the gspi serial data input pin of the GV7704. the 16-bit command and data words from the host processor ar e shifted into the device on the rising edge of sclk when the cs pin is low. 4.9.3 sdout pin the sdout pin is the gspi serial data output of the GV7704. all data transfers out of th e GV7704 to the host processor occur from this pin. by default at power up or after system reset, the sdout pin provides a non-clocked path directly from the sdin pin, only when the cs pin is low, except during the gspi data word portion for read operations to the device. when the cs pin is high, the sdout pin will be in a high-impedance state. table 4-11: audio mute controls address register parameter description channel 0: 488d h channel 1: 548d h channel 2: 608d h channel 3: 6c8d h aud_ext_config_ reg mute_0_1 high = channels 0 & 1 are muted low = channels 0 & 1 are not muted mute_2_3 high = channels 2 & 3 are muted low = channels 2 & 3 are not muted
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 31 of 52 semtech www.semtech.com for read operations, the sdout pin is used to output data read from an internal configuration and status register (csr) when cs is low. data is shifted out of the device on the falling edge of sclk, so that it can be read by the host processor on the subsequent sclk rising edge. the current drive strength of the sdout pin can be adjusted using the gspi_sdout_drv_strength_sel bit. 4.9.4 sclk pin the sclk pin is the gspi serial data shift cl ock input to the device, and must be provided by the host processor. serial data is clocked into the GV7704 sdin pin on the rising edge of sclk. serial data is clocked out of the device fr om the sdout pin on the falling edge of sclk (read operation). sclk is ignored when cs is high. 4.9.5 command word description all gspi accesses are a minimum of 48 bits in length (a 16-bit command word, a 16-bit extended address field, and a 16-bit data wo rd) and the start of each access is indicated by the high-to-low transition of the chip select (cs ) pin of the GV7704. the format of the command word and data words are shown in figure 4-13 . data received immediately foll owing this high-to-low transi tion will be interpreted as a new command word. 4.9.5.1 r/ w bit - b15 command word this bit indicates a read or write operation. when r/w is set to 1, a read operation is indica ted and data is read from the register specified by the address field of the command word. when r/w is set to 0, a write operation is indica ted and data is wri tten to the register specified by the address field of the command word. 4.9.5.2 broadcast all - b14 command word this bit must always be set to 0. 4.9.5.3 emem - b13 command word this bit must always be set to 1. 4.9.5.4 autoinc - b12 command word when autoinc is set to 1, auto-increment read or write access is enabled. in auto-increment mode, the device automati cally increments the register address for each contiguous read or write access, starti ng from the address de fined in the address field of the command word.
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 32 of 52 semtech www.semtech.com the internal address is incr emented for each 16-bit read or write access until a low-to-high transition on the cs pin is detected. when autoinc is set to 0, single read or write access is required . auto-increment write must not be used to update values in host_config. 4.9.5.5 unit address - b11:b5 command word the 7 bits of the unit address field of th e command word should always be set to 0. 4.9.5.6 address - b4:b0 command wo rd, b15:b0 extended address the address word consists of bits [4:0] of the command word, plus another 16 bits [15:0] from the extended address word. the total command and data word format, including the extended address, is shown in figure 4-13 below. figure 4-13: command and data word format 4.9.6 data word description the data word portion of the gspi access cons ists of an 8-bit repe tition code, followed by an 8-bit read or write access payload. all registers in the GV7704 are 8 bits long, however since gspi write commands are required to be 16 bits long, the data word will have the same byte repeated. for example, to write fc h to a register within the csr, the 16-bit data word of the gspi command should be fcfc h . msb lsb 1 autoinc 0 0 0 00 command word unit address address[20:16] 0 d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 data word r / w address[15:0] a16 a17 a18 a19 a20 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 repetition code payload (read/write data) 0 0
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 33 of 52 semtech www.semtech.com 4.9.7 gspi transaction timing figure 4-14: gspi exte rnal interface timing r/w 0 sclk write mode sdin signal is looped out on sdout sdout 1 a3 a2 a1 a0 r/w 0 sclk read mode sdin signal is looped out on sdout sdout 1 a3 a2 a1 a0 read data is output on sdout d0 r/w 0 sdin 1 0 0 0 0 0 a3 a2 a1 a0 d15 d14 d 13 d 12 d11 d10 d9 d8 r/w 0 sdin 1 auto_ inc a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d15 d 14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d15 d14 d13 d 12 d11 d10 d9 d8 t 0 t 8 t 2 t 3 t 1 t 9 t 6 t 5 t 7 t 4 sclk sdin command command data command command data sdout t cmd x t 9 a14 a13 00000 a14 a13 00000 a14 a13 00000 a14 a13 32 sclk cycles 16 sclk cycles 32 sclk cycles 16 sclk cycles cs cs cs auto_ inc auto_ inc auto_ inc high-z high-z high-z table 4-12: gspi timing parameters parameter symbol min typ max units cs low before sclk rising edge t 0 2.0 ns sclk frequency 55 mhz sclk period t 1 18.2 ns sclk duty cycle t 2 40 50 60 % input data setup time t 3 2.7 ns sclk idle time write t 4 41.7 ns sclk idle time read t 5 162 ns inter-command delay time t cmd 162 ns sdout after sclk falling edge t 6 7.5ns cs high after final sclk falling edge t 7 0.0 ns input data hold time t 8 1.0 ns
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 34 of 52 semtech www.semtech.com 4.9.8 single read/write access single read/write access timing fo r the gspi interface is shown in figure 4-15 and figure 4-16 . when performing a single read or write access, one data word is read from/written to the device per access. each access is a mi nimum of 48-bits long, consisting of a command word, an extended address, and a single data word. the read or write cycle begins with a high-to-lo w transition of the cs pin. the read or write access is terminated by a low-to-high transition of the cs pin. the maximum interface clock frequency (sclk) is 55mhz and the inter-command delay time indicated in the figures as t cmd , is a minimum of 162ns. for read access, the time from the last bit of the command word to the start of the data output, as defined by t 5 , corresponds to no less than 162ns. figure 4-15: gspi write timing C single write access figure 4-16: gspi read timing C single read access 4.9.9 auto-increment read/write access auto-increment read/write access timing for the gspi interface is shown in figure 4-17 and figure 4-18 . auto-increment mode is enab led by the setting of the autoinc bit of the command word. cs high time t 9 57.0 ns sdin to sdout combinational delay 5.0ns table 4-12: gspi timing parameters (continued) parameter symbol min typ max units sclk cs sdin sdout command [15:0] command [15:0] data [15:0] data [15:0] command [31:16] command [31:16] x x t cmd command [31:16] command [31:16] sclk cs sdin sdout command [15:0] command [15:0] data [15:0] t 5 command [31:16] command [31:16]
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 35 of 52 semtech www.semtech.com in this mode, multiple data words can be read from/written to th e device using only one starting address. each acce ss is initiated by a high-t o-low transition of the cs pin, and consists of a command word and one or more data words. the internal address is automatically incremen ted after the first read or writ e data word, and continues to increment until the read or write access is terminated by a low-to-high transition of the cs pin. note: writing to host_config using auto -increment access is not allowed. the maximum interface clock frequency (sclk) is 55mhz and the inter-command delay time indicated in the diagram as t cmd , is a minimum of 162ns. for read access, the time from the last bit of the first command word to the start of the data output of the first data word as defined by t 5 , will be no less than 162ns. all subsequent read data accesses will not be subject to this delay during an auto-increment read. figure 4-17: gspi write timing C auto-increment figure 4-18: gspi read timing C auto-increment 4.10 jtag the GV7704 provides an ieee 1 149.1-compliant jtag tap in terface for bo undary scan test and debug. the GV7704 tap interface consists of the tc k clock input, trst, tdi and tms inputs, and the tdo output as defined in the standard. tms and tdi inputs are clocked with respect to the rising edge of tck and the tdo output with respect to the falling edge of tck. sclk cs sdin sdout command [15:0] command [15:0] data 1 data 1 data 2 data 2 command [31:16] command [31:16] sclk cs sdin sdout t 5 command [15:0] command [15:0] data 1 data 2 command [31:16] command [31:16]
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 36 of 52 semtech www.semtech.com 4.11 power supply and reset timing figure 4-19: power supply and reset timing note: to ensure correct digital functionalit y of the part the 1.8v supply must be powered before the 1.2v supply. timing not critical vdd18 powering precedes vdd12 vdd18 vdd12 reset csr (control & status registers) t_resetb t_gspi_ready reset states csr accessible by gspi 1.8v 1.2v 1.8v t_resetb >= 10ms t_gspi_ready = 10s indeterminate states
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 37 of 52 semtech www.semtech.com 5. register map table 5-1: GV7704 register descri ptions channel controls address register name parameter name bit slice r/w reset value description 4078 h gspi_sdout_drv_ strength_sel_reg gspi_sdout_drv_ strength_sel 0:0 rw 1 b gspi sdout drive strength select. 1 b = high drive strength 0 b = low drive strength 44f1 h (ch 0) 50f1 h (ch 1) 5cf1 h (ch 2) 68f1 h (ch 3) input_termination_ reg input_termination 0:0 rw 1 b sets the receive input termination impedance. termination is to vdd18. 0 b = 50 1 b = 75 44f2 h (ch 0) 50f2 h (ch 1) 5cf2 h (ch 2) 68f2 h (ch 3) power_up_driver_reg pu_drvn 0:0 rw 0 b power up control for the sdo_n path 0 b = power down 1 b = power up pu_drvp 1:1 rw 0 b power up control for the sdo_p path 0 b = power down 1 b = power up 44f3 h (ch 0) 50f3 h (ch 1) 5cf3 h (ch 2) 68f3 h (ch 3) p2s_clk_en_reg p2s_clk_en 0:0 rw 0 b parallel to serial converter in transmit path clock buffer enable 0 b = clocks in the p2s are turned off 1 b = clocks in the p2s are enabled 44f4 h (ch 0) 50f4 h (ch 1) 5cf4 h (ch 2) 68f4 h (ch 3) p2s_rstb_reg p2s_rstb 0:0 rw 0 b parallel to serial converter in transmit path reset 0 b = hold p2s flops in reset 1 b = p2s not in reset 44f5 h (ch 0) 50f5 h (ch 1) 5cf5 h (ch 2) 68f5 h (ch 3) cdr_tx_clk_en_reg cdr_tx_clk_en 0:0 rw 0 b enable for transmit path clock 0 b = turn off half rate clock to the p2s in the transmit path 1 b = turn on half rate clock to the p2s in the transmit path 44f6 h (ch 0) 50f6 h (ch 1) 5cf6 h (ch 2) 68f6 h (ch 3) sdo_50_en_reg sdo_50_en 0:0 rw 0 b sdo_p/n 50 termination enable 0 b = 75 termination 1 b = 50 termination
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 38 of 52 semtech www.semtech.com 4469 h (ch 0) 5069 h (ch 1) 5c69 h (ch 2) 6869 h (ch 3) datalane_fifo_ctrl_ reg datalane_fifo_wr_ flush 0:0 rw 0 b initiates a flush from the writer side on the fifo. active high. datalane_fifo_rd_ start_thresh 5:1 rw 4 h number or items that need to be written to fifo before the read process starts. 4823 h (ch 0) 5423 h (ch 1) 6023 h (ch 2) 6c23 h (ch 3) video_ctrl_override_ reg disable_video_lane 5:4 rw 0 h x0 b = lane n is enabled 11 b = lane n is enabled 01 b = lane n is disabled regardless of the presence of a valid signal 4824 h (ch 0) 5424 h (ch 1) 6024 h (ch 2) 6c24 h (ch 3) audio_ctrl_override_ reg disable_audio 1:0 rw 0 h x0 b = channel n audio is enabled 11 b = channel n audio is enabled 01 b = channel n audio is disabled 4825 h (ch 0) 5425 h (ch 1) 6025 h (ch 2) 6c25 h (ch 3) audio_samp_freq_ override_reg audio_samp_freq 2:1 rw 0 h manually specifies the audio sampling rate when audio_samp_freq_manual_ mode = 1 00 b = 48khz 01 b = 44.1khz 10 b = 32khz 11 b = reserved audio_samp_freq_ manual_mode 0:0 rw 0 b this mode only needs to be enabled if the audio sampling information is not present in the stream id packets. if the incoming signal is transmitted by a gv7700, the information will be present and this mode does not need to be enabled. 1 b = the audio sampling frequency will be manually specified according to audio_samp_freq. 0 b = the device will automatically detect the audio sampling frequency present within the stream id of the video signal. 482c h (ch 0) 542c h (ch 1) 602c h (ch 2) 6c2c h (ch 3) gen_video_cfg_0_ reg sd_hdb 1:1 ro 0 b when high, indicates that the incoming signal is 270mb/s. when low, indicates that the incoming signal is 1.485gb/s. table 5-1: GV7704 register descriptions channel controls (continued) address register name parameter name bit slice r/w reset value description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 39 of 52 semtech www.semtech.com 4863 h (ch 0) 5463 h (ch 1) 6063 h (ch 2) 6c63 h (ch 3) extract_stream_id_ reg1 extract_stream_id_ byte1 7:0 ro 0 h extract byte 1 information for the packet on ds1 (first udw in the stream id packet) 4864 h (ch 0) 5464 h (ch 1) 6064 h (ch 2) 6c64 h (ch 3) extract_stream_id_ reg2 extract_stream_id_ byte2 7:0 ro 0 h extract byte 2 information for the packet on ds1 (first udw in the stream id packet) 4865 h (ch 0) 5465 h (ch 1) 6065 h (ch 2) 6c65 h (ch 3) extract_stream_id_ reg3 extract_stream_id_ byte3 7:0 ro 0 h extract byte 3 information for the packet on ds1 (first udw in the stream id packet) 4866 h (ch 0) 5466 h (ch 1) 6066 h (ch 2) 6c66 h (ch 3) extract_stream_id_ reg4 extract_stream_id_ byte4 7:0 ro 0 h extract byte 4 information for the packet on ds1 (first udw in the stream id packet) 4867 h (ch 0) 5467 h (ch 1) 6067 h (ch 2) 6c67 h (ch 3) extract_stream_id_ reg5 extract_stream_id_ byte5 7:0 ro 0 h extract byte 5 information for the packet on ds1 (first udw in the stream id packet) 4868 h (ch 0) 5468 h (ch 1) 6068 h (ch 2) 6c68 h (ch 3) extract_stream_id_ reg6 extract_stream_id_ byte6 7:0 ro 0 h extract byte 6 information for the packet on ds1 (first udw in the stream id packet) 487d h (ch 0) 547d h (ch 1) 607d h (ch 2) 6c7d h (ch 3) ins_id_byte1_reg ins_id_byte1 7:0 rwc 0 h identification code byte 1 487e h (ch 0) 547e h (ch 1) 607e h (ch 2) 6c7e h (ch 3) ins_id_byte2_reg ins_id_byte2 7:0 rwc 0 h identification code byte 2 table 5-1: GV7704 register descriptions channel controls (continued) address register name parameter name bit slice r/w reset value description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 40 of 52 semtech www.semtech.com 488d h (ch 0) 548d h (ch 1) 608d h (ch 2) 6c8d h (ch 3) aud_ext_config_reg mute_2_3 3:3 rw 0 h audio mute for channels 2 & 3. when high, the device will set the ch1_aout_2_3 serial output to 0. mute_0_1 2:2 rw 0 h audio mute for channels 0 & 1. when high, the device will set the ch1_aout_0_1 serial output to 0. 488e h (ch 0) 548e h (ch 1) 608e h (ch 2) 6c8e h (ch 3) audio_did_9_8_reg audio_did_9_8 1:0 rw 0 h bits 8-9 of the audio packet did to be extracted. 488f h (ch 0) 548f h (ch 1) 608f h (ch 2) 6c8f h (ch 3) audio_did_7_0_reg audio_did_7_0 7:0 rw 0 h bits 0-7 of the audio packet did to be extracted. 4892 h (ch 0) 5492 h (ch 1) 6092 h (ch 2) 6c92 h (ch 3) audio_detect_0_reg audio_grp_detect 7:0 ro 0 h audio group detection status. 10000000 b = group 8 did detected 01000000 b = group 7 did detected 00100000 b = group 6 did detected 00010000 b = group 5 did detected 00001000 b = group 4 did detected 00000100 b = group 3 did detected 00000010 b = group 2 did detected 00000001 b = group 1 did detected 4893 h (ch 0) 5493 h (ch 1) 6093 h (ch 2) 6c93 h (ch 3) audio_detect_1_reg audio_detect_1 0:0 ro 0 b when high, indicates that an ancillary data packet having a did matching audio_did has been detected in the video. 48c6 h (ch 0) 54c6 h (ch 1) 60c6 h (ch 2) 6cc6 h (ch 3) anc_packet_did_9_ 8_reg anc_packet_did_9_8 1:0 rw 0 h 10-bit did that the device will seek and extract udws from. anc_packet_did is considered a static signal. bits [9:8] table 5-1: GV7704 register descriptions channel controls (continued) address register name parameter name bit slice r/w reset value description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 41 of 52 semtech www.semtech.com 48c7 h (ch 0) 54c7 h (ch 1) 60c7 h (ch 2) 6cc7 h (ch 3) anc_packet_did_7_ 0_reg anc_packet_did_7_0 7:0 rwc 0 h 10-bit did that the device will seek and extract udws from. anc_packet_did is considered a static signal. bits [7:0] 48c8 h (ch 0) 54c8 h (ch 1) 60c8 h (ch 2) 6cc8 h (ch 3) anc_extract_status_ reg anc_packet_ imcomplete 2:2 ro 0 b when high, indicates that the packet the device has received contains more than 16 udws, which exceeds the maximum allowable amount. anc_extract_ update_toggle 1:1 rocw 0 b set high when the device has finished extracting all the words from the desired packet type. writing 1 to this bit clears the status. anc_extract_idle 0:0 ro 0 b 1 b = device is not currently extracting words from the desired did packet. 0 b = device is currently extracting words from the did packet specified by ans_packet_did 48c9 h (ch 0) 54c9 h (ch 1) 60c9 h (ch 2) 6cc9 h (ch 3) anc_packet_sdid_9_8_ reg anc_packet_sdid_ 9_8 1:0 ro 0 h secondary data identification word extracted from the ancillary data packet. bits [9:8] 48ca h (ch 0) 54ca h (ch 1) 60ca h (ch 2) 6cca h (ch 3) anc_packet_sdid_7_0_ reg anc_packet_sdid_ 7_0 7:0 ro 0 h secondary data identification word extracted from the ancillary data packet. bits [7:0] 48cb h (ch 0) 54cb h (ch 1) 60cb h (ch 2) 6ccb h (ch 3) anc_packet_dc_9_8_ reg anc_packet_dc_9_ 8 1:0 ro 0 h data word count extracted from the ancillary data packet. represents the number of user data words (udw) in the ancillary data packet. bits [9:8] 48cc h (ch 0) 54cc h (ch 1) 60cc h (ch 2) 6ccc h (ch 3) anc_packet_dc_7_0_ reg anc_packet_dc_7_ 0 7:0 ro 0 h data word count extracted from the ancillary data packet. represents the number of user data words (udw) in the ancillary data packet. bits [7:0] 48cd h (ch 0) 54cd h (ch 1) 60cd h (ch 2) 6ccd h (ch 3) anc_packet_udw0_ 9_8_reg anc_packet_udw0_ 9_8 1:0 ro 0 h user data word 0 extracted from the ancillary data packet. bits [9:8] table 5-1: GV7704 register descriptions channel controls (continued) address register name parameter name bit slice r/w reset value description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 42 of 52 semtech www.semtech.com 48ce h (ch 0) 54ce h (ch 1) 60ce h (ch 2) 6cce h (ch 3) anc_packet_udw0_ 7_0_reg anc_packet_udw0_ 7_0 7:0 ro 0 h user data word 0 extracted from the ancillary data packet. bits [7:0] 48cf h (ch 0) 54cf h (ch 1) 60cf h (ch 2) 6ccf h (ch 3) anc_packet_udw1_ 9_8_reg anc_packet_udw1_ 9_8 1:0 ro 0 h user data word 1 extracted from the ancillary data packet. bits [9:8] 48d0 h (ch 0) 54d0 h (ch 1) 60d0 h (ch 2) 6cd0 h (ch 3) anc_packet_udw1_ 7_0_reg anc_packet_udw1_ 7_0 7:0 ro 0 h user data word 1 extracted from the ancillary data packet. bits [7:0] 48d1 h (ch 0) 54d1 h (ch 1) 60d1 h (ch 2) 6cd1 h (ch 3) anc_packet_udw2_ 9_8_reg anc_packet_udw2_ 9_8 1:0 ro 0 h user data word 2 extracted from the ancillary data packet. bits [9:8] 48d2 h (ch 0) 54d2 h (ch 1) 60d2 h (ch 2) 6cd2 h (ch 3) anc_packet_udw2_ 7_0_reg anc_packet_udw2_ 7_0 7:0 ro 0 h user data word 2 extracted from the ancillary data packet. bits [7:0] 48d3 h (ch 0) 54d3 h (ch 1) 60d3 h (ch 2) 6cd3 h (ch 3) anc_packet_udw3_ 9_8_reg anc_packet_udw3_ 9_8 1:0 ro 0 h user data word 3 extracted from the ancillary data packet. bits [9:8] 48d4 h (ch 0) 54d4 h (ch 1) 60d4 h (ch 2) 6cd4 h (ch 3) anc_packet_udw3_ 7_0_reg anc_packet_udw3_ 7_0 7:0 ro 0 h user data word 3 extracted from the ancillary data packet. bits [7:0] 48d5 h (ch 0) 54d5 h (ch 1) 60d5 h (ch 2) 6cd5 h (ch 3) anc_packet_udw4_ 9_8_reg anc_packet_udw4_ 9_8 1:0 ro 0 h user data word 4 extracted from the ancillary data packet. bits [9:8] table 5-1: GV7704 register descriptions channel controls (continued) address register name parameter name bit slice r/w reset value description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 43 of 52 semtech www.semtech.com 48d6 h (ch 0) 54d6 h (ch 1) 60d6 h (ch 2) 6cd6 h (ch 3) anc_packet_udw4_ 7_0_reg anc_packet_udw4_ 7_0 7:0 ro 0 h user data word 4 extracted from the ancillary data packet. bits [7:0] 48d7 h (ch 0) 54d7 h (ch 1) 60d7 h (ch 2) 6cd7 h (ch 3) anc_packet_udw5_ 9_8_reg anc_packet_udw5_ 9_8 1:0 ro 0 h user data word 5 extracted from the ancillary data packet. bits [9:8] 48d8 h (ch 0) 54d8 h (ch 1) 60d8 h (ch 2) 6cd8 h (ch 3) anc_packet_udw5_ 7_0_reg anc_packet_udw5_ 7_0 7:0 ro 0 h user data word 5 extracted from the ancillary data packet. bits [7:0] 48d9 h (ch 0) 54d9 h (ch 1) 60d9 h (ch 2) 6cd9 h (ch 3) anc_packet_udw6_ 9_8_reg anc_packet_udw6_ 9_8 1:0 ro 0 h user data word 6 extracted from the ancillary data packet. bits [9:8] 48da h (ch 0) 54da h (ch 1) 60da h (ch 2) 6cda h (ch 3) anc_packet_udw6_ 7_0_reg anc_packet_udw6_ 7_0 7:0 ro 0 h user data word 6 extracted from the ancillary data packet. bits [7:0] 48db h (ch 0) 54db h (ch 1) 60db h (ch 2) 6cdb h (ch 3) anc_packet_udw7_ 9_8_reg anc_packet_udw7_ 9_8 1:0 ro 0 h user data word 7 extracted from the ancillary data packet. bits [9:8] 48dc h (ch 0) 54dc h (ch 1) 60dc h (ch 2) 6cdc h (ch 3) anc_packet_udw7_ 7_0_reg anc_packet_udw7_ 7_0 7:0 ro 0 h user data word 7 extracted from the ancillary data packet. bits [7:0] 48dd h (ch 0) 54dd h (ch 1) 60dd h (ch 2) 6cdd h (ch 3) anc_packet_udw8_ 9_8_reg anc_packet_udw8_ 9_8 1:0 ro 0 h user data word 8 extracted from the ancillary data packet. bits [9:8] table 5-1: GV7704 register descriptions channel controls (continued) address register name parameter name bit slice r/w reset value description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 44 of 52 semtech www.semtech.com 48de h (ch 0) 54de h (ch 1) 60de h (ch 2) 6cde h (ch 3) anc_packet_udw8_ 7_0_reg anc_packet_udw8_ 7_0 7:0 ro 0 h user data word 8 extracted from the ancillary data packet. bits [7:0] 48df h (ch 0) 54df h (ch 1) 60df h (ch 2) 6cdf h (ch 3) anc_packet_udw9_ 9_8_reg anc_packet_udw9_ 9_8 1:0 ro 0 h user data word 9 extracted from the ancillary data packet. bits [9:8] 48e0 h (ch 0) 54e0 h (ch 1) 60e0 h (ch 2) 6ce0 h (ch 3) anc_packet_udw9_ 7_0_reg anc_packet_udw9_ 7_0 7:0 ro 0 h user data word 9 extracted from the ancillary data packet. bits [7:0] 48e1 h (ch 0) 54e1 h (ch 1) 60e1 h (ch 2) 6ce1 h (ch 3) anc_packet_udw10_ 9_8_reg anc_packet_udw10_ 9_8 1:0 ro 0 h user data word 10 extracted from the ancillary data packet. bits [9:8] 48e2 h (ch 0) 54e2 h (ch 1) 60e2 h (ch 2) 6ce2 h (ch 3) anc_packet_udw10_ 7_0_reg anc_packet_udw10_ 7_0 7:0 ro 0 h user data word 10 extracted from the ancillary data packet. bits [7:0] 48e3 h (ch 0) 54e3 h (ch 1) 60e3 h (ch 2) 6ce3 h (ch 3) anc_packet_udw11_ 9_8_reg anc_packet_udw11_ 9_8 1:0 ro 0 h user data word 11 extracted from the ancillary data packet. bits [9:8] 48e4 h (ch 0) 54e4 h (ch 1) 60e4 h (ch 2) 6ce4 h (ch 3) anc_packet_udw11_ 7_0_reg anc_packet_udw11_ 7_0 7:0 ro 0 h user data word 11 extracted from the ancillary data packet. bits [7:0] 48e5 h (ch 0) 54e5 h (ch 1) 60e5 h (ch 2) 6ce5 h (ch 3) anc_packet_udw12_ 9_8_reg anc_packet_udw12_ 9_8 1:0 ro 0 h user data word 12 extracted from the ancillary data packet. bits [9:8] table 5-1: GV7704 register descriptions channel controls (continued) address register name parameter name bit slice r/w reset value description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 45 of 52 semtech www.semtech.com 48e6 h (ch 0) 54e6 h (ch 1) 60e6 h (ch 2) 6ce6 h (ch 3) anc_packet_udw12_ 7_0_reg anc_packet_udw12_ 7_0 7:0 ro 0 h user data word 12 extracted from the ancillary data packet. bits [7:0] 48e7 h (ch 0) 54e7 h (ch 1) 60e7 h (ch 2) 6ce7 h (ch 3) anc_packet_udw13_ 9_8_reg anc_packet_udw13_ 9_8 1:0 ro 0 h user data word 13 extracted from the ancillary data packet. bits [9:8] 48e8 h (ch 0) 54e8 h (ch 1) 60e8 h (ch 2) 6ce8 h (ch 3) anc_packet_udw13_ 7_0_reg anc_packet_udw13_ 7_0 7:0 ro 0 h user data word 13 extracted from the ancillary data packet. bits [7:0] 48e9 h (ch 0) 54e9 h (ch 1) 60e9 h (ch 2) 6ce9 h (ch 3) anc_packet_udw14_ 9_8_reg anc_packet_udw14_ 9_8 1:0 ro 0 h user data word 14 extracted from the ancillary data packet. bits [9:8] 48ea h (ch 0) 54ea h (ch 1) 60ea h (ch 2) 6cea h (ch 3) anc_packet_udw14_ 7_0_reg anc_packet_udw14_ 7_0 7:0 ro 0 h user data word 14 extracted from the ancillary data packet. bits [7:0] 48eb h (ch 0) 54eb h (ch 1) 60eb h (ch 2) 6ceb h (ch 3) anc_packet_udw15_ 9_8_reg anc_packet_udw15_ 9_8 1:0 ro 0 h user data word 15 extracted from the ancillary data packet. bits [9:8] 48ec h (ch 0) 54ec h (ch 1) 60ec h (ch 2) 6cec h (ch 3) anc_packet_udw15_ 7_0_reg anc_packet_udw15_ 7_0 7:0 ro 0 h user data word 15 extracted from the ancillary data packet. bits [7:0] table 5-1: GV7704 register descriptions channel controls (continued) address register name parameter name bit slice r/w reset value description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 46 of 52 semtech www.semtech.com 48ed h (ch 0) 54ed h (ch 1) 60ed h (ch 2) 6ced h (ch 3) anc_packet_cs_9_8_ reg anc_packet_cs_9_ 8 1:0 ro 0 h cs word extracted from the ancillary data packet. equal to the nine least significant bits of the sum of the nine least significant bits of the data identification (did) word, the data block number (dbn)/ secondary data identification word (sdid), the data count (dc) word, and all user data words (udw) in the packet. bits [9:8] 48ee h (ch 0) 54ee h (ch 1) 60ee h (ch 2) 6cee h (ch 3) anc_packet_cs_7_0_ reg anc_packet_cs_7_ 0 7:0 ro 0 h cs word extracted from the ancillary data packet. bits [7:0] 48ef h (ch 0) 54ef h (ch 1) 60ef h (ch 2) 6cef h (ch 3) output_block_cfg_ reg bt656_enable 0:0 rw 0 b 1 b = device generates the bt656 10-bit ycbcr multiplexed video format 0 b = device generates the default smpte 10-bit ycbcr multiplexed video format 48f4 h (ch 0) 54f4 h (ch 1) 60f4 h (ch 2) 6cf4 h (ch 3) tx_word_clk_ enable_reg tx_word_clk_ enable 0:0 rw 0 b used in the procedure to enable sdo. see section 4.3.2.1 for details 492c h (ch 0) 552c h (ch 1) 612c h (ch 2) 6d2c h (ch 3) parallel_video_out _drv_strength_sel_ reg parallel_video_ out_drv_ strength_sel 0:0 rw 0 b parallel video output (pclk, hout, vout, fout, dout[9:0]) drive strength select. 1 b = high drive strength 0 b = low drive strength table 5-1: GV7704 register descriptions channel controls (continued) address register name parameter name bit slice r/w reset value description
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 47 of 52 semtech www.semtech.com 6. application information 6.1 typical application circuit figure 6-1: typical appl ication circuit (part 1) 4.7k 0 10k 10k 0 10k 0 100k 1f 10k GV7704 reset gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd cs 0 sys_rst sys_rst n/c n/c rsvd rsvd c26 10nf c27 10nf c28 10nf c29 10nf c30 10nf c31 1f c32 10nf c33 10nf c34 10nf c35 10nf c36 10nf c37 10nf c38 10nf c39 10nf c40 10nf c41 1f c42 10nf c43 10nf c44 10nf c45 10nf c46 10nf c47 10nf c48 10nf c49 10nf c50 10nf c51 1f c52 10nf c53 10nf c54 10nf c55 10nf c56 10nf c57 10nf c58 10nf c59 1f vdda12_1 vdda12_2 vdda12_3 vdda12_4 vdda12_5 vdd12_d_1 vdd12_d_2 vdd12_d_3 vdd12_d_4 vdd12_d_5 vdd12_d_6 vdd12_d_7 vdd12_d_8 vdd12_d_9 vdda18_1 vdda18_2 vdda18_3 vdda18_4 vdda18_5 vdda18_6 vdda18_7 vdda18_8 vdda18_9 vdd18_d_1 vdd18_d_2 vdd18_d_3 vdd18_d_4 vdd18_d_5 vdd18_d_6 trst tms tck tdi tdo sdin sclk sdout rbias ext_fw gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc_a_1v8 vcc_a_1v2 vcc1v2 vcc1v2 vcc1v8 vcc1v8 vcc1v8 vcc1v8 vcc1v8 r15 r14 c25 r20 dnp r18 r19 r21 r16 spi_cs_GV7704_1 spi_sdin_GV7704 spi_clk_GV7704 spi_dout_GV7704_1 spi_cs_GV7704_1 spi_sdin_GV7704 spi_clk_GV7704 spi_dout_GV7704_1 r17 r23 k4 d8 d5 l3 k8 l1 c1 c2 k5 k9 d9 k10 j6 j10 j9 g11 g5 h5 h10 j5 f5 e10 e9 e6 d10 n3 f10 g10 e2 g1 g2 j1 j2 k3 m1 m2 e1 d3 b2 b1 a3 m5 l4 n5 l5 d4 b5 a5 c4 c5 e5 e4 f4 g4 h4 j4 f6 f7 f8 g6 g7 g8 h6 h7 h8 b3 c3 e3 f3 g3 h3 j3 l2 m3 e7 e8 f9 g9 h9 j7 j8 u3-1 r25 r2 vdd18_d_7 gnd ext_fw: high to load external firmware low to load from internal firmware
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 48 of 52 semtech www.semtech.com figure 6-2: typical appl ication circuit (part 2) figure 6-3: alternative catx input circuit 4.7f 4.7f 4.7f 4.7f 1f 1f 1f 1f 75 75 75 75 GV7704 GV7704 75 1f 1f 4.7f 75 4.7f 4.7f 4.7f 1f 1f 75 75 GV7704 GV7704 sdi input0 sdi input2 sdi input3 sdi input1 sdi input0 loop-through sdi input2 loop-through sdi input1 loop-through sdi input3 loop-through ch0_dout9 ch0_dout8 ch0_dout7 ch0_dout6 ch0_dout5 ch0_dout4 ch0_dout3 ch0_dout2 ch0_dout1 ch0_dout0 ch0_dout9 ch0_dout8 ch0_dout7 ch0_dout6 ch0_dout5 ch0_dout4 ch0_dout3 ch0_dout2 ch0_dout1 ch0_dout0 ch1_dout9 ch1_dout8 ch1_dout7 ch1_dout6 ch1_dout5 ch1_dout4 ch1_dout3 ch1_dout2 ch1_dout1 ch1_dout0 ch1_dout9 ch1_dout8 ch1_dout7 ch1_dout6 ch1_dout5 ch1_dout4 ch1_dout3 ch1_dout2 ch1_dout1 ch1_dout0 ch2_dout9 ch2_dout8 ch2_dout7 ch2_dout6 ch2_dout5 ch2_dout4 ch2_dout3 ch2_dout2 ch2_dout1 ch2_dout0 ch2_dout9 ch2_dout8 ch2_dout7 ch2_dout6 ch2_dout5 ch2_dout4 ch2_dout3 ch2_dout2 ch2_dout1 ch2_dout0 ch3_dout9 ch3_dout8 ch3_dout7 ch3_dout6 ch3_dout5 ch3_dout4 ch3_dout3 ch3_dout2 ch3_dout1 ch3_dout0 ch3_dout9 ch3_dout8 ch3_dout7 ch3_dout6 ch3_dout5 ch3_dout4 ch3_dout3 ch3_dout2 ch3_dout1 ch3_dout0 ch0_pclk f_ch0 v_ch0 h_ch0 ch1_pclk f_ch1 v_ch1 h_ch1 ch2_pclk f_ch2 v_ch2 h_ch2 ch3_pclk f_ch3 v_ch3 h_ch3 i2s_wclk_ch0 i2s_aclk_ch0 i2s_d_a1/2_ch0 i2s_d_a3/4_ch0 i2s_wclk_ch1 i2s_aclk_ch1 i2s_d_a1/2_ch1 i2s_d_a3/4_ch1 i2s_wclk_ch2 i2s_aclk_ch2 i2s_d_a1/2_ch2 i2s_d_a3/4_ch2 i2s_wclk_ch3 i2s_aclk_ch3 i2s_d_a1/2_ch3 i2s_d_a3/4_ch3 ch0_pclk ch0_fout ch0_vout ch0_hout ch2_pclk ch2_fout ch2_vout ch2_hout ch1_pclk ch1_fout ch1_vout ch1_hout ch3_pclk ch3_fout ch3_vout ch3_hout ch0_wclk ch0_aclk ch0_aout1_2 ch0_aout3_4 ch2_wclk ch2_aclk ch2_aout1_2 ch2_aout3_4 ch1_wclk ch1_aclk ch1_aout1_2 ch1_aout3_4 ch3_wclk ch3_aclk ch3_aout1_2 ch3_aout3_4 ch0_sdip ch0_sdin ch2_sdip ch2_sdin ch1_sdip ch1_sdin ch3_sdip ch3_sdin ch0_sdop ch0_sdon ch2_sdop ch2_sdon ch1_sdop ch1_sdon ch3_sdop ch3_sdon n1 n2 c62 c61 n4 m4 r30 r33 c66 c68 ucbbje20-1 m11 m10 l10 n10 l9 m9 n9 l8 m8 n8 n11 n13 m12 n12 k6 l6 m6 n6 gnd gnd gnd gnd d11 d12 d13 e11 e12 e13 f11 f12 f13 g13 c13 c12 b13 c11 a7 b7 c7 d7 c9 b9 c10 b10 a10 a11 b11 a13 a12 b12 b8 c8 a9 b6 a6 a8 d6 c6 j11 j12 j13 k12 k11 m13 l13 j12 l11 k13 m7 l7 k7 g12 h13 h12 h11 n7 k1 k2 c73 c71 r40 h1 h2 c76 r44 c79 ucbbje20-1 ucbbje20-1 j8 ucbbje20-1 ucbbje20-1 ucbbje20-1 ucbbje20-1 d1 d2 f1 f2 r32 r3 c67 c69 a1 a2 a4 b4 r42 c77 r43 c78 c72 c74 c65 c64 ucbbje20-1 GV7704 ch0_sdip n1 n2 1 2 3 4 5 6 7 8 reserved for power reserved for ucc 1f 1f rj45 white/orange white/green blue green white/blue white/brown brown orange ch0_sdin
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 49 of 52 semtech www.semtech.com 7. packaging information 7.1 package dimensions figure 7-1: GV7704 package dimensions 1234 56 78910111213 a b c d e f g h j k l m n top view pin a1 corner ea d b aaa (4x) symbol common dimensions package: body size: ball pitch: total thickness: mold thickness: substrate thickness: ball diameter: stand off: ball width: package edge tolerance: mold flatness: coplanarity: ball offset (package): ball offset (ball): ball count: edge ball center to center: x x x y y y lbga e d ee ed 11.000 11.000 0.800 0.800 a m s a1 b aaa bbb ddd eee fff n e1 d1 1.470 0.100 0.700 ref. 0.560 ref. 0.300 0.160 ~ 0.260 0.270 ~ 0.370 0.050 0.100 0.080 0.150 0.050 169 9.600 9.600 seating plane side view c 5. s m a a1 3. bbb c ddd c e1 ee a b c d e f g h j k l m n 1 2 3 4 5 6 7 8 9 10 11 12 13 bottom view a1 corner ?eee ?ddd m m c c ab ?b (n x) d1 ed notes: 1. dimensioning and tolerancing per asme y14.5m C 1994. 2. solder ball position designation per jesd 95C1, sppC010. 3. this dimension includes stand-off height, package body thickness and lid height, but does not include attached features, e.g., external heatsink or chip capacitors. an integral heatslug is not considered an attached feature. 4. dimension is measured at the maximum solder ball diameter, parallel to primary datum c. 5. primary datum c and seating plane are defined by the spherical crowns of the solder balls. 6. all dimensions are in millimeters.
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 50 of 52 semtech www.semtech.com 7.2 recommended pcb footprint figure 7-2: GV7704 pcb footprint 7.3 marking diagram figure 7-3: GV7704 marking diagram 0.8 0.35 note: all dimensions in millimeters 9.6 9.6 GV7704 xxxxe3 yyww pin 1 id xxxx - last 4 digits of assembly lot. e3 - pb-free & green indicator yyww - date code
GV7704 preliminary data sheet rev.3 pds-060376 september 2015 51 of 52 semtech www.semtech.com 7.4 solder reflow profile figure 7-4: maximum pb-free solder reflow profile 7.5 packaging data 7.6 ordering information 25c 150c 200c 217c 260c 250c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3c/sec max 6c/sec max table 7-1: GV7704 packaging data parameter value package type/dimensions/pad pitch 169 wb-bga 11mm x 11mm, 0.8mm pitch moisture sensitivity level (msl) 3 junction to case thermal resistance, j-c 12.1c/w junction to ambient thermal resistance (zero airflow), j-a 35.4c/w junction-to-top of package characterization, j-t 0.14c/w junction to board thermal resistance, j-b 25.7c/w pb-free and rohs compliant yes table 7-2: GV7704 ordering information part package GV7704-ibe3 169-pin lbga (176 pc/tray)
important notice information relating to this product and the application or design described herein is believed to be reliable, however such in formation is provided as a guide only and semtech assumes no liability for any errors in this document, or for the application or design des cribed herein. semtech reserves the right to make changes to the product or this document at any time without notice. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. semtech warrants performance of its products to the specifications applicable at the time of sale, and all sales are made in accordance with semtechs standard ter ms and conditions of sale. semtech products are not designed, intended, authorized or warr anted to be suitable for use in life-support applications, devices or systems, or in nuclear applications in which the failure could be reasonably expected to result in personal injury, loss of life or severe property or environmental dama ge. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damage s and attorney fees which could arise. the semtech name and logo are registered trademarks of the se mtech corporation. all other trademarks and trade names mentioned may be marks and names of semtech or their respective companies. semtec h reserves the right to make changes to, or discontinue any pro ducts described in this document without further notice. semtech makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose. all rights reserved. ? semtech 2015 GV7704 preliminary data sheet rev.3 pds-060376 september 2015 52 of 52 semtech 52 contact information semtech corporation 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111, fax: (805) 498-3804 www.semtech.com

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